In the field of ICs, data buses are often provided for conveying data within the ICs. Particularly, data buses are commonly employed for memory device ICs, for example for non volatile memory devices. Non volatile memory devices are commonly used for storing information that has to be preserved in the absence of an electrical power source supplying the memory device. In particular, a flash memory typically includes a matrix of cells, each one consisting of a MOS transistor with a floating gate. The transistor is programmed by injecting an electrical charge onto the corresponding floating gate; on the contrary, the transistor is erased by removing the electrical charge from the corresponding floating gate. The electrical charge stored on the floating gate of a transistor modifies its threshold voltage, in such a way as to define different conductivity states and, consequently, different logic values. For example, in memory devices storing a single bit per cell, wherein each cell is capable of memorizing a single bit of information, the generic cell can assume two different threshold voltage values (associated with the two logic values “0” and “1”). In memory devices storing two bits per cell, the generic memory cell can instead assume four different threshold voltage values (associated with the four logic values “00”, “01”, “10”, and “11”).
The memory device further includes a bit line for each column of the matrix, and a word line for each row. A single cell is placed at the crossing of the bit line with the word line to which the cell belongs.
For a better selectivity in erasing, the matrix of cells can be partitioned in sectors, each one being capable of being individually erased; the various sectors can be positioned in such a way to form column of sectors.
The operation of reading the memory cells includes biasing them according to proper operating conditions, and sensing the (read) current that they drain. Particularly, the operations for sensing the read current are performed by a plurality of sense amplifiers, which are arranged in the proximity of the area in the silicon chip wherein the matrix of memory cells is integrated. Referring for example to a multilevel flash memory device having two bits per cell, the sense amplifier receives a current value corresponding to the conductivity state of the memory cell, and outputs two signals that represent, at the end of the reading operation, the two bits corresponding to the state. When the reading is finished, the two bits are stored (in a volatile way) into two bistable elements (e.g., flip-flops), and transmitted outside the area dedicated to the memory matrix toward output circuits, by two properly driven signal lines. The two signal lines coming from a sense amplifier are arranged side by side with those coming from the other sense amplifiers of the memory device, so as to form a data bus that connects the plurality of sense amplifiers with the output circuits. In the case of a memory that is capable of storing more than two bits per cell, the number of signal lines correspondingly increases.
Each signal line forming the data bus, realized with a metallic material, typically aluminum, is affected by a parasitic capacitive load toward ground and a capacitive coupling with the adjacent signal lines. The capacitive coupling dominates the parasitic capacitive load of the bus (i.e., the parasitic capacitance of the bus lines toward ground), because of the size scaling of the circuit devices due to modern technologies. In particular, the total capacitance due to the contribution of all the lines of the data bus of a memory device may reach a value on the order of hundreds of picofarads (pF).
Because of the high capacitive load of the signal lines belonging to the data bus, the switching of the signal lines involves a high electrical power dissipation, and may provoke electrical noise (for example, voltage spikes) that superimposes on the voltages supplying the circuit. The resulting electrical noise is dangerous, because it is capable of invalidating the reading operation of the cell. The flip-flops connected to the outputs of the sense amplifiers, properly clocked, have, among others, the purpose of avoiding the switching of the signal lines during the reading operations, and the purpose of allowing it only at the end of the reading operations, when the electrical noise is no longer able to interfere with the result of the reading.
The reading operation in certain memory devices is advantageously performed simultaneously on a relatively high number of cells, and a very large data word (e.g., a 128-bit data word) is stored in the flip flops. Such a data word cannot be made available at the outside of the memory all at one time, but the access (of a “synchronous” type, because it is synchronized by the clock signals of the flip-flops) to the data stored in the flip-flops can be performed in a parallel way, for example in groups of 8/16 bits at a time, depending on the parallelism of the memory. Particularly, the output circuits are sequentially connected, by the corresponding signal lines, to the output of 8/16 flip-flops at a time. The delay between the reading of each data group and the subsequent data group depends on the length of the data bus lines, because the output signals of the flip-flops necessitate a propagation time for propagating along the respective signal lines.
The ever-increasing demand for increased reading speeds has therefore lead to placing the flip-flops far from the sense amplifiers, and not near them, i.e., the flip-flops have been positioned in correspondence to the ends of the data bus lines, outside the area dedicated to the memory matrix. In this way, the data stored in the flip-flops connected to the signal lines can be made available to the output circuits more rapidly, without having to wait for the propagation of the signals along the data bus (this propagation occurs only during the first access, when the data word read from the cells has to be stored into the flip-flops).
Conversely, the demand for shorter and shorter asynchronous access times involves the use of architectures providing independent sense amplifier modules per each memory sector, or per groups thereof. Because of the increase in the number of sense amplifiers, if the flip-flops were positioned close to the outputs of the sense amplifiers, the number of necessary flip-flops would drastically increase, with a consequent excessive waste of silicon chip area. By placing the flip-flops at the end of the signal lines of the data bus (which can be common to several memory sectors, through a proper multiplexing), the number thereof can be reduced.
Unfortunately, placing the flip-flops at the end of the signal lines of the data bus makes it no longer possible to take advantage of the flip-flops presence for preventing the signal lines of the data bus from switching during the reading, and it is necessary to take care of the induced electrical noise that superimpose on the supply voltages, caused by the switching of the signal lines during the reading operations because, during the reading operation of a cell, the outputs of the corresponding sense amplifier are not stable. In fact, the outputs can switch several times, or slowly pass from one state to the other before reaching a final logic state (for example, the state “1”, typically associated with a voltage value equal to the supply voltage, e.g., Vdd=3V, and the state “0”, typically associated with ground). In the absence of flip-flops directly connected to the outputs of the sense amplifiers that “mask” the switching of the signal lines during the reading operation, problems of power consumption and electrical noise are faced, which can critically affect the reading operation itself. In fact, with the parasitic capacitance values, a voltage switching of a signal line of the data bus from ground to the supply voltage of 3 V is capable of producing a high current spike (even as high as 100 mA), with a consequent drop in the supply voltage value, which is capable of invalidate the reading.
Thus, a solution is necessary for the problems of electrical noise and power consumption that is compatible with the placement of the flip-flops so as to be no more directly in correspondence to the sense amplifier outputs, but outside the area dedicated to the memory matrix.
A possible solution is proposed in U.S. Pat. No. 6,442,069, in which a data transmission architecture of differential type is described; in this way, the voltage excursions of the signal lines are limited, and the problems of electrical noise and power consumption are reduced.
We have observed that such a structure is however expensive in terms of silicon chip area. In fact, transmitting the data by differential signals requires adding a reference signal line for each signal line of the data bus, and a final structure for converting the differential signal into a logic signal, with reference to the ground.
A different solution is proposed in U.S. Pat. No. 6,351,150, which provides for transmitting a datum on the signal line only when the datum varies between two readings, so as to reduce the switching. This solution is implemented using a “domino” logic (exploiting timing signals that establish a precharging phase and an evaluation phase of the datum).
However, we have observed that such a structure has the disadvantages of still having a flip-flop connected to the input of each signal line, necessitating a timing signal, and having floating nodes along the signal line, sensitive to possible electrical disturbances.
A further solution is proposed in U.S. Pat. No. 6,442,089, which describes a “differential-domino” logic. In this way no more flip-flops are connected to the input of the signal lines, but this solution has the drawbacks typical of differential transmission (e.g., transmission lines that are duplicated), plus the managing of a system having a timing signal.